MVME162-201 Modular Motorola

Description

MVME162-201

Programming Model

This section defines the programming model for the control and status

registers (CSRs) in the MCECC pair. The base address of the CSRs is hard

coded to the address $FFF43000 for the MCECC pair on the first

mezzanine board and $FFF43100 for the MCECC pair on the second

mezzanine board. The CSRs for the two MCECCs appear at the same

address, (one on D16-D31, the other on D00-D15).

Hardware automatically duplicates the values that are written to the CSRs

in the upper MCECC (the one that connects to D16-D31) to the lower

MCECC (the one that connects to D0-D15). Hence Software only needs

to write to the control registers in the upper MCECC. This duplicating

function can be disabled by software for test purposes.

A Note on the “Differences with MEMC040” information

in this section

In some other MVME product families, the MCECC corresponds to a

parity memory controller, the MEMC040, with which it shares a group of

similarly-defined registers. For reference purposes, differences between

these registers are briefly documented in this section as described below,

but the MEMC040 is not used on any MVME162LX boards.

The first eight registers of the MCECC pair are those whose register map

was made to look as similar as possible to the map for the same eight

registers contained in the MEMC040. Where there are differences, they

are noted. The remaining 18 registers contain functions unique to the

MCECC pair.

MVME162-010A

MVME162-201