TRICONEX 3005

Description

Main Processor Modules
Model 3005 Main Processors (MP) are
available for Tricon v9.6 and later
systems. For detailed specifications,
see the Planning and Installation Guide
for Tricon Systems.
Three MPs must be installed in the
Main Chassis of every Tricon system.
Each MP independently communicates
with its I/O subsystem and executes the
user-written control program.
Sequence of Events (SOE)
and Time Synchronization
During each scan, the MPs inspect
designated discrete variables for state
changes known as events. When an
event occurs, the MPs save the current
variable state and time stamp in the
buffer of an SOE block.
If multiple Tricon systems are
connected by means of NCMs, the time
synchronization capability ensures a
consistent time base for effective SOE
time-stamping. See page 72 for more
information.
Diagnostics
Extensive diagnostics validate the
health of each MP, I/O module and
communication channel. Transient
faults are recorded and masked by the
hardware majority-voting circuit.
Persistent faults are diagnosed and the
errant module is hot-replaced.
MP diagnostics perform these tasks:
• Verify fixed-program memory and
static RAM
• Test all basic processor and floatingpoint instructions and operating
modes
• Validate user memory by means of
the TriBus hardware-voting
circuitry
• Verify the shared memory interface
with each I/O communication
processor and channel
• Verify handshake and interrupt
signals between the CPU, each I/O
communication processor and
channel
• Check each I/O communication
processor and channel
microprocessor, ROM, shared
memory access and loopback of RS485 transceivers
• Verify the TriClock and TriBus
interfaces

Feature Description
Microprocessor Motorola MPC860, 32 bit, 50 MHz
Memory • 16 MB DRAM (non-battery backed-up)
• 32 KB SRAM, battery backed-up
• 6 MB Flash PROM
Tribus Communication Rate • 25 megabits per second
• 32-bit CRC protected
• 32-bit DMA, fully isolated
I/O Bus and Communication Bus
Processors
• Motorola MPC860
• 32 bit
• 50 MHz